Who Do I Partition A Service Breaker From Wiring

This section describes how to determine if at that place is a existent need for excursion sectionalisation or some other solution, such every bit irresolute your HIL configuration, should be considered.

The first pace of excursion partition is to analyze the circuit and determine if at that place is actually a need for circuit partitioning. This sounds obvious, but in some cases other possibilities tin be considered every bit well, such as a different device configuration. In nearly cases circuit partitioning is needed because of one of the following reasons:

There are as well many converters in the circuit - the overall weight of the converters exceeds the limit
There are too many contactors in the circuit - the overall number of contactors exceeds the limit
Matrix retention overloaded - most ordinarily due to a big number of switches in the circut
The simulation time step is too big

A complementary sit-in of practical cases where we need to consider these resource limits is also available in the Video Knowledgebase and as function of the HIL Fundamentals course.

Too many converters in the circuit

I of the nearly common reasons to perform excursion sectionalization is there are too many converters in the model. Converters are characterized past their weight. Processing cores usually support converters up to weight 3 (for example a three phase converter), but at that place are some processor configurations that back up converters up to weight 4, such equally HIL604 in Configuration 4, or C4. In the example model shown in Effigy 1, a boost converter (weight = one) and a 3 phase converter (weight = 3) are present. This means that the overall weight of power electronic converters is 4. If this circuit is compiled for HIL604 C1, the compiler will report an error that the overall weight of converters exceeds the limit. While at kickoff glance it seems that we cannot avert circuit partitioning into ii cores, we could instead switch to HIL604 C4 to solve this upshot without the need of excursion partitioning. In some cases information technology is better to alter the configuration than to partition the excursion. The compiler written report for the same model, compiled for both HIL604 C1 and HIL604 C4 is shown in Effigy 2.

Figure ane . DC-DC converter and iii-phase 2-level converter

Figure 2 . Compiler report snapshot for HIL604 C1 and C4 respectively

Another example where at that place are multiple converters in the model is a 3 phase back-to-back converter shown in Figure 3. The overall weight of converters in the model is 6. There is no HIL configuration that supports converters up to weight 6 per single core, thus circuit partitioning must exist performed in this model.

Effigy 3 . Three-phase 2-level dorsum-to-dorsum converter

Too many contactors in the circuit

The number of ideal contactors supported per cadre is 6 for all device configurations. If the number of contactors exceeds this number, excursion partitioning is unavoidable. This case normally occurs in microgrid models where there are lot of protection devices and excursion breakers. An case of a model with 7 contactors is shown in Figure 4.

Effigy 4 . Seven contactors in a circuit

Matrix memory overload

In the case shown in Figure 5, it seems that none of the hardware resource is overloaded – the number of contactors is less than 6, the overall weight of the converter is iii. However, if the model is compiled for HIL604 C1, an error message volition be reported equally shown on the left side of Figure seven, stating that the matrix memory utilization of cadre 1 is 269%. Partitioning the model as shown in Figure 6 is i manner to solve this issue. This will result in a model that runs in two cores with a 1μs simulation time step. In this example, however, changing the HIL604 configuration to C4 will solve the problem without excursion sectionalization. The compiler report for HIL604 C4 is shown on the correct side of Figure 7.

Figure v . Iii-phase two-level converter with a lot of additional contactors

Figure six . Iii-phase two-level converter with a lot of additional contactors - partitioned

Figure seven . Compiler written report snapshot for HIL604 C1 and C4

Simulation time pace too large

By partitioning the circuit the ciphering is distributed beyond multiple cores and/or devices and lower simulation rates can exist accomplished. This can exist demonstrated by the IEEE thirteen node jitney example model in the Example Explorer. Currently this model runs with a fixed timestep of 4μs. If it would be partitioned in two cores, it would run at 1μs.